1. Field of the Invention
The present invention relates to a voltage reference generator, and more particularly to a start-up circuit for a reference voltage circuit that restarts the reference voltage circuit when a reference voltage drops under a predetermined level due to noises or change of a supply voltage.
2. Description of the Conventional Art
FIG. 1 is a schematic circuit diagram of a conventional reference voltage generator.
As shown therein, the conventional reference voltage generator is composed of a start-up circuit unit 10 enabled by a reset signal RESET in power up and operating a following reference voltage generating unit 20 and the reference voltage generating unit 20 operated by a signal outputted from the start-up circuit unit 10 and generating a reference voltage in accordance with a power supply voltage Vcc.
The start-up circuit unit 10 includes a first NMOS transistor 11 having a gate for receiving the reset signal RESET and a drain connected with the reference voltage generating unit 20, and a second NMOS transistor 12 having a drain connected with a source of the first NMOS transistor 11, a gate commonly connected with the drain thereof and a source connected with a ground voltage Vss.
The reference voltage generating unit 20 includes a first and a second PMOS transistors 21, 22 constituting a current mirror and each source is connected with the power supply voltage Vcc, a first and a second NMOS transistors 23, 24 connected with the first and the second PMOS transistors 21, 22, respectively, and constituting a current mirror, and a resistor 25 connected between the first NMOS transistor 23 and the ground voltage Vss. Now, the operation of the conventional reference voltage generator will be described.
First, when power is externally applied, power supply circuits in a chip device operate and thus power-up is carried out.
The transistors 21, 22, 23, 24 of the reference voltage generating unit 20 are initially in an off state, and a voltage of a node N20 of the first PMOS transistor 21 is determined higher than a voltage difference (Vcc-.vertline.Vtp.vertline.) between the power supply voltage Vcc and a threshold voltage Vtp of the PMOS transistor 21.
While the power-up is carried out, the reset signal RESET is applied to the gate of the first NMOS transistor 11 of the start-up circuit unit 10 at a high level for a certain period, that is a predetermined initial period for which a system voltage increases from the ground voltage Vss to the power supply voltage Vcc.
Accordingly, the first NMOS transistor 11 is turned on and a potential of the node N20 connected with the reference voltage generating unit 20 is pulled down. Thus, the first and the second PMOS transistors 21, 22 are turned on and a reference voltage Vref is generated.
However, in the conventional voltage generator when the power supply voltage Vcc becomes instantaneously unstable due to conditions such as external noises, the reference voltage Vref can not be a sufficient voltage level. In this case, it is impossible for the conventional start-up circuit unit 10 to restart the reference voltage generating unit 20.